1. Field of the Invention
The present invention relates to the fabrication of integrated circuit devices and, more particularly, to a method of integrating a salicide process and a self-aligned contact process in the fabrication of integrated circuits.
2. Description of the Related Art
In the fabrication of integrated circuit devices, a self-aligned contact (SAC) process is often used to define the space between adjacent gate electrodes and limit it in order to reduce cell size, especially as applied to the fabrication of memory products, such as trench DRAM, stacked DRAM, and FLASH memory. Logic products are often produced using a salicide (self-aligned silicide) process, in which a refractory metal layer is deposited on a silicon layer and then annealed. The underlying silicon reacts with the refractory metal layer to produce a silicide overlying the gate electrode and source/drain regions. The silicided regions of gate electrode and source/drain regions have lower resistance than nonsilicided regions, and thereby improve circuit performance. Referring to FIG. 1, a gate structure is composed of a silicon nitride cap layer 1, a polycide layer 2, and a doped-polysilicon layer 3. Using SAC process, a contact hole 4 is formed between two adjacent gate structures. However, in the application of the logic process, there are issues, such as lower circuit performance and a problem with surface channel of the PMOS device, associated with the gate structure. Seeking to solve the shortcomings with conventional technique, the salicide process is only provided to periphery areas. Alternatively, the SAC process is avoided.
With respect to the fabrication of embedded memory, memory devices and logic circuits for addressing the memory devices are formed on the same chip. It is desired to find a method of integrating the salicide process and SAC process on a wafer so as to achieve both high logic performance and high-density memory for embedded memory. Referring to FIGS. 2A to 2F, a method of integrating the salicide process and SAC process is disclosed by U.S. Pat. No. 5,998,252. As shown in FIG. 2A, a semiconductor substrate 10 has a plurality of field oxide regions 12, and is divided by a dashed line into a logic circuit area 5 and a memory device area 7. In the memory device area 7, a plurality of gate structures 22 and source/drain regions 24 are fabricated on the semiconductor substrate 10. Each of the gate structures 22 is composed of a gate insulating layer 14, a polysilicon layer 16, a silicon oxide layer 18, and a silicon nitride cap layer 20. In the logic circuit area 5, a plurality of gate structures 28 and source/drain regions 30 are formed on the semiconductor substrate 30. Each of the gate structures 28 is composed of a gate insulating layer 14, a polysilicon layer 16, and a silicon nitride spacer 26 covered on the sidewall of the gate structure 28.
Referring to FIGS. 2C and 2B, a conformal protection layer 32 is applied over the exposed surface of the semiconductor substrate 10, and a photoresist layer 34 is patterned on the protection layer 32 in the memory device area 7. Next, using the photoresist layer 34 as a mask, the protection layer 32 in the logic circuit area 5 is removed, thus the gate structures 28 and the source/drain regions 30 in the logic circuit area 5 are exposed. Referring to FIGS. 2D and 2E, a refractory metal layer 36, preferably made of Ti or TiN, is deposited on the exposed surface of the semiconductor substrate 10, and then the refractory metal layer 36 reacts with underlying silicon through rapid thermal anneal (RTA) process. As a result, a silicide layer 38 is formed on the top of the gate structure 28 and the exposed surface of the source/drain region 30 in the logic circuit area 5.
Referring to FIG. 2F, the SAC process is performed in the memory device area 7. An inter-layer dielectric 37 is deposited on the semiconductor substrate 10, and then the inter-layer dielectric 37 and the protection layer 32 positioned between adjacent gate structures 22 are removed by a dry etching process. Therefore, a contact hole 39 is completed wherein the source/drain region 24 between adjacent gate structures 22 is exposed.
In the aforementioned method, the salicide process is only applied to the logic circuit area 5. That means the silicide 38 cannot be formed on the polysilicon layer 16 in the memory device area 7 at the same time when the silicide 38 is formed on the gate structure 28 and the source/drain region 30 in the logic circuit area 5. None of the above inventions and patents, taken either singularly or in combination, is seen to describe the instant invention as claimed. Thus, a method of integrating the salicide process and the SAC process solving the aforementioned problems is desired.
The present invention is a method of integrating the salicide process and the self-aligned contact (SAC) process to form a silicide on the gate electrode in a memory device area at the same time that the silicide is formed on the gate electrode and the source/drain regions in a periphery area. The method of integrating the salicide process and SAC process is provided on a semiconductor substrate that is divided into a memory device area or a periphery area for fabricating embedded memory and trench DRAM. An oxide layer is formed on the exposed surface, and then a plurality of spacers is formed on the sidewalls of the gate electrodes respectively. Sequentially, a barrier layer and a buffering layer are formed on the exposed surface. Next, the buffering layer and the barrier layer are removed from the top of the gate electrodes to expose the oxide layer. The exposed oxide layer and the underlying gate electrodes are then removed until the gate electrode reaches a predetermined height. The salicide process is performed to form a silicide on the exposed surface of the gate electrodes and simultaneously on the source/drain regions in the periphery area. Next, a gate cap layer is formed on the silicide overlying the gate electrodes. After forming an inter-layer dielectric on the exposed surface, the self-aligned contact process is performed to form a contact hole to exposes the source/drain region positioned between adjacent gate electrodes in the memory device area.
In the first modification, the gate electrodes are fabricated as stacked gate electrodes are fabricated through more masks and etching processes for the application of FLASH memory. Also, a combination structure of an oxide spacer and a nitride spacer is employed on the sidewall of the stacked gate structure for solving the leakage problem and preventing the source/drain region from pitting phenomenon.
In the second modification, since the oxide layer is possibly removed to expose active regions in an etching environment, a cap layer formed on the top of the gate electrodes is required prior to removing the gate electrodes.
In the third modification, a photoresist layer in the periphery area is required after performing the etch-back process on the buffering layer in order to avoid the pitting phenomenon of the source/drain regions from the insufficient etching effect on the oxide layer. Therefore, after etching the gate electrodes, the height of the gate electrode in the periphery area is higher than the height of the gate electrode in the memory device area.
In the fourth modification, an ion-implantation process that is performed on the gate electrodes and the source/drain regions is performed in the memory device area at the beginning, and then performed on the semiconductor substrate in the periphery area to form a source/drain region surrounding the gate electrode in the periphery area after etching the gate electrodes.
In the fifth modification, a cap layer is required prior to the formation of the gate cap layer in order to prevent the silicide from over-etching during the etch-back process on the gate cap layer.
Accordingly, it is a principal object of the invention to provide a method to integrate the salicide process and the SAC process to achieve both high logic performance and high-density memory.
It is another object of the invention to provide the application of FLASH memory.
Yet another object of the invention is to solve the leakage problem and protect the source/drain region from pitting.
It is a further object of the invention to avoid pitting of the source/drain regions from the insufficient etching effect of the oxide layer.
Still another object of the invention is to prevent the silicide from over-etching during the etch-back process on the gate cap layer.
These and other objects of the present invention will become readily apparent upon further review of the following specification and drawings.